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w49f002u 256k 8 cmos flash memory publication release date: april 2000 - 1 - revision a2 general description the w49f002u is a 2 - megabit, 5 - volt only cmos flash memory organized as 256k 8 bits. the device can be programmed and erased in - system with a standard 5v power supply. a 12 - volt v pp is not required. the unique cell architecture of the w49f002u results in fast program/erase operations with extremely low current consumption (compared to other comparable 5 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 5 - volt operations: - 5 - volt read - 5 - volt erase - 5 - volt program fast program operation: - byte - by - byte programming: 35 m s (typ.) fast erase operation: 100 ms (t yp.) fast read access time: 70/90/120 ns endurance: 10k cycles (typ.) ten - year data retention hardware data protection one 16k byte boot block with lockout protection two 8k byte parameter blocks two main memory blocks (96k, 128k) bytes low power consumption - active current: 25 ma (typ.) - standby current: 20 m a (typ.) automatic program and erase timing with internal v pp generation end of program or erase detection - t oggle bit - data polling latched address and data ttl compatible i/o jedec standard byte - wide pinouts available packages: 3 2 - pin dip and 32 - pin tsop and 32 - pin - plcc
w49f002u - 2 - pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 gnd a7 a6 a5 a4 a3 a2 a1 a0 a16 a15 a12 v we a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 dd a17 32-pin dip reset 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 g n d d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 oe a10 ce dq7 a 1 2 a 1 6 v d d / w e a 1 5 32-pin plcc a 1 7 / r e s e t 32-pin tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a15 a12 a7 a6 a5 a4 v we a14 a13 a8 dd a11 a9 a16 a17 reset a3 a2 a1 a0 dq0 dq1 dq2 gnd oe a10 ce dq7 dq6 dq5 dq4 dq3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 block diagram control output buffer decoder ce oe we a0 . . a17 . . dq0 v dd v ss dq7 3ffff 20000 1ffff 38000 37fff 3a000 39fff 00000 3c000 3bfff reset parameter block2 8k bytes boot block 16k bytes parameter block1 8k bytes main memory block2 128k bytes main memory block1 96k bytes pin description symbol pin name reset reset a0 - a17 address inputs dq0 - dq7 data inputs/outputs ce chip enable oe output enable we write enable v dd power supply gnd ground
w49f002u p ublication release date: april 2000 - 3 - revision a2 functional descripti on read mode the read operation of the w49f002u is controlled by ce and oe , both of which have to be low for the host to obtain data from the outputs. ce is used for device selection. when ce is high, the chip is de - selected and only standby power will be consumed. oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce or oe is high. refer to the timing waveforms for further details. reset operation the reset input pin can be used in some application. when reset pin is at high state, the device is in normal operation mode. when reset pin is at low state, it will halts the device and all outputs are at high impedance state. as the high state re - asserted to the reset pin, the device will return to read or standby mode, it depends on the control signals. when the system drives the reset pin low for at least a period of 500 ns, the device immediately ter minates any operation in progress duration of the reset pulse. the other function for reset pin is temporary reset the boot block. by applying the 12v to reset pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. boot block operation there is one 16k - byte boot block in this device, which can be used to store boot code. it is located in the last 16k bytes with the address range of the boot block is 3c000(hex) to 3ffff(hex ).see command code sequence for boot block lockout enable for the specific code. once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed with the regular program ming method. once the boot block programming lockout feature is activated, the chip erase function can no longer erase the boot block. there is one condition that the lockout feature can be overridden. just apply 12v to reset pin, the lockou t feature will temporarily be inactivated and the block can be erased/programmed. once the reset pin return to ttl level, the lockout feature will be activated again. in order to detect whether the boot block feature is set on the 16k - bytes block, users can perform software command code sequence: enter the product identification mode (see command codes for identification/boot block lockout detection for specific code), and then read from address "0002 (hex)". if the dq 0 of output data is "1, " the boot block programming lockout feature is activated; if the dq0 of output data is "0 ," the lockout feature is inactivated and the block can be erased/programmed. to return to normal operation, perform a three - byte command code sequence (or an alter nate single - byte command) to exit the identification mode. for the specific code, see command code for identification/boot block lockout detection. chip erase operation the chip - erase mode can be initiated by a six - byte command code sequence. after the co mmand loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed as fast as 100 ms (typical). the host system is not required to provide any control or timing during this operation. the entire memory a rray will be erased to ff hex. by the chip erase
w49f002u - 4 - operation if the boot block programming lockout feature is not activated. once the boot block lockout feature is activated, the whole chip erase function will erase the two main memory blocks and the two par ameter blocks but not the boot block. the device will automatically return to normal read mode after the erase operation. data polling and/or toggle bits can be used to detect end of erase cycle. sector erase operation there are four sectors: two main memo ry blocks and two parameters blocks which can be erased individually by initiating a six - byte command code sequence. sector address is latched on the falling edge of we signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of we in this cycle. after the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed as fast as 100 ms (typical). the host system does not require to provide any control or timing during this operation. the device will automatically return to normal read mode after the erase operation. data polling and/or toggle bits can be used to detect the end of erase cycle. when different sector address is loaded in the sixth cycle for sector erase command, the correspondent sectors will be erased automatically; that these sections will be erased independedntly. for detail sector to be erased information, please refer to the table of command definition . program ope ration the w49f002u is programmed on a byte - by - byte basis. program operation can only change logical data "1" to logical data "0". the erase operation (changed entire data in two main memory blocks and two parameter blocks and/or boot block from "0" to "1" ) is needed before programming. the program operation is initiated by a 4 - byte command code sequence (see command codes for byte programming). the device will internally enter the program operation immediately after the byte - program command is entered. the internal program timer will automatically time - out (50 m s max. - t bp ). once completed, the device returns to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle. hardware data protection the integrity of the data s tored in the w49f002u is also hardware protected in the following ways: (1) noise/glitch protection: a we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming operation is inhibited when v dd is less than 2.5v typical. (3) write inhibit mode: forcing oe low, ce high, or we high will inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. (4) v dd power - on delay: when v dd has reached its sense level, the device will automatically time - out 5 ms before any write (erase/program) operation. data polling (dq 7 ) - write status detection the w49f002u includes a data polling feature t o indicate the end of a program or erase cycle. when the w49f002u is in the internal program or erase cycle, any attempt to read dq 7 of the last byte loaded will receive the complement of the true data. once the program or erase cycle is completed, dq 7 wi ll show the true data. note that dq 7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
w49f002u publication release date: april 2000 - 5 - revision a2 toggle bit (dq 6 ) - write status detection in addition to data polling, the w49f002u provides an other method for determining the end of a program cycle. during the internal program or erase cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. product identification the product id operation outputs the manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorith ms. the manufacturer and device codes can be accessed by software or hardware operation. in the software access mode, a three - byte (or jedec 3 - byte) command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer c ode da(hex). a read from address 0001h outputs the device code 0b(hex). the product id operation can be terminated by a three - byte command code sequence or an alternate one - byte command code sequence (see command definition table). in the hardware access mode, access to the product id is activated by forcing ce and oe low, we high, and raising a9 to 12 volts. table of operating m odes operating mode selection (v hh = 12v 5 % ) mode pins reset ce oe we address dq. read v ih v il v il v ih a in dout write v ih v il v ih v il a in din standby v ih v ih x x x high z write inhibit v ih x v il x x high z/dout v ih x x v ih x high z/dout output disable v ih x v ih x x high z reset mode v il x x x x high z product id v ih v il v il v ih a0 = v il ; a1 - a17 = v il ; a9 = v hh manufacturer code da (hex) v ih v il v il v ih a0 = v ih ; a1 - a17 = v il ; a9 = v hh device code 0b (hex)
w49f002u - 6 - table of command def inition (1) command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 secto r erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3) 30 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in boot block lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 55 55 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 notes: 1. address format: a14 - a0 (hex); data format: dq7 - dq0 (hex) 2. either one of the two product id exit commands can be used. 3. sa means: sector a ddress if sa is within 3c000 to 3ffff (boot block address range), and the boot block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 100ns. if the boot block programming lockout feature is not activated, this command will erase boot block. if sa is within 3a000 to 3bfff (parameter block1 address range), this command will erase pb1. if sa is within 38000 to 39fff (parameter block2 address range), this command will erase pb2. if sa is within 20 000 to 37fff (main memory block1 address range), this command will erase mmb1. if sa is within 00000 to 1ffff (main memory block2 address range), this command will erase mmb2.
w49f002u publication release date: april 2000 - 7 - revision a2 command codes for byte program command sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h a0h 3 write programmed - address programmed - data byte program flow chart byte program command flow load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data din to programmed- address exit pause t bp notes for software program code: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w49f002u - 8 - command codes for chip erase byte s equence address data 1 write 5555h aah 2 write 2aaah 55h 3 write 5555h 80h 4 write 5555h aah 5 write 2aaah 55h 6 write 5555h 10h chip erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa exit load data 10 to address 5555 pause t ec notes for chip erase: data format: dq7 - dq0 ( hex) address format: a14 - a0 (hex)
w49f002u publication release date: april 2000 - 9 - revision a2 command codes for sector erase byte sequence address data 1 write 5555h aah 2 write 2aaah 55h 3 write 5555h 80h 4 write 5555h aah 5 write 2aaah 55h 6 write sa* 30h sector erase acquis ition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 30 to address sa* exit pause t ec notes for chip erase: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex) sa : for details, see the page 6 .
w49f002u - 10 - command codes for product identification and boot block lockout detection byte sequence software product ident ification/boot block lockout detection entry software product identification/boot block lockout detection exit(6) address data address data 1 write 5555 aa 5555h aah 2 write 2aaa 55 2aaah 55h 3 write 5555 90 5555h f0h pause 10 m s pause 10 m s softwa re product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 0000 data = da read address = 0001 read address = 0002 data =in dq0= "1" / "0" (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 m m notes for software product identification/boot block lockout detection: (1) data format: dq7 - dq0 (hex); address format: a14 - a0 (hex) (2) a1 - a17 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) if the output data in dq0= " 1 " the boot block programming lockout feature is activated ; if the output data in dq0 = " 0 ," the lockout feature is inactivated and the boot block can be programmed. (5) the device returns to standard operation mode. (6) optional 1 - byte cycle (write f0 hex at xxxx address) can be used to exit the product identification/boot block lockout detection.
w49f002u publication release date: april 2000 - 11 - revision a2 command codes for boot block lockout enable byte sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h 80h 3 write 5555h aah 4 write 2aaah 55h 5 write 5555h 40h pause t bp boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 exit pause t bp notes for boot block lockout enable: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w49f002u - 12 - dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +7.0 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential except oe - 0.5 to v dd +1.0 v transient voltage (<20 ns ) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on oe pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc operatin g characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i cc ce = oe = v il , we = v ih , all dqs open address inputs = v il /v ih , at f = 5 mhz - 25 50 ma standby v dd current (ttl input) i sb 1 ce = v ih , all dqs open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 ce = v dd - 0.3v, all dqs open other inputs = v dd - 0 .3v/gnd - 20 100 m a input leakage current i li v in = gnd to v dd - - 10 m a output leakage current i lo v out = gnd to v dd - - 10 m a input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0 .45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v
w49f002u publication release date: april 2000 - 13 - revision a2 power - up timing parameter symbol typical unit power - up to read operation t pu . read 100 m s power - up to write operation t pu . write 5 ms capacitance (v dd = 5.0v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditions parameter conditions input pulse levels 0v to 3.0v input rise/fall time < 5 ns input/output timing level 1 .5v/1.5v output load 1 ttl gate and c l = 100 pf for 120 ns; c l = 30 pf for 70 ns /90 ns ac test load and waveform +5v 1.8k 1.3k d out w w 30 pf for 70ns / 90ns (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output 100 pf for 120ns
w49f002u - 14 - ac characteristics, continued read cycle timing parameters (v cc = 5.0v 10 % , v cc = 0v, t a = 0 to 70 c) parameter sym. w49f002u - 70 w49f002u - 90 w49f002u - 120 unit min. max. min. max. min. max. read cycle time t rc 70 - 90 - 120 - ns chip enable access time t ce - 70 - 90 - 120 ns address access time t aa - 70 - 90 - 120 ns output enable ac cess time t oe - 35 - 40 - 50 ns ce low to active output t clz 0 - 0 - 0 - ns oe low to active output t olz 0 - 0 - 0 - ns ce high to high - z output t chz - 25 - 25 - 30 ns oe high to h igh - z output t ohz - 25 - 25 - 30 ns output hold from address change t oh 0 - 0 - 0 - ns write cycle timing parameters parameter symbol min. typ. max. unit address setup time t as 0 - - ns address hold time t ah 50 - - ns we and ce setup time t cs 0 - - ns we and ce hold time t ch 0 - - ns oe high setup time t oes 0 - - ns oe high hold time t oeh 0 - - ns ce pulse width t cp 100 - - ns we pulse width t wp 100 - - ns we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 10 - - ns byte programming time t bp - 35 50 m s erase cycle time t ec - 0.1 0.2 s note: all ac timing s ignals observe the following guidelines for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w49f002u publication release date: april 2000 - 15 - revision a2 ac characteristics, continued data polling and toggle bit timing parameter s parameter sym. w49f002u - 70 w49f002u - 90 w49f002u - 120 unit min. max. min. max. min. max. oe to data polling output delay t oep - 35 - 40 - 50 ns ce to data polling output delay t cep - 70 - 90 - 120 ns oe to toggle bit output delay t oet - 35 - 40 - 50 ns ce to toggle bit output delay t cet - 70 - 90 - 120 ns timing waveforms read cycle timing diagram address a17-0 dq7-0 data valid data valid high-z ce oe we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z
w49f002u - 16 - timing waveforms, continued we controlled command write cycle timing diagram address a17-0 dq7-0 data valid ce oe we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh ce controlled command write cycle timing diagram high z data valid ce oe we dq7-0 t as t ah t cph t oeh t dh t ds t cp t oes address a17-0
w49f002u publication release date: april 2000 - 17 - revision a2 timing waveforms, continued program cycle timing diagram address a17-0 byte 0 byte 1 byte 2 internal write start dq7-0 ce oe we byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 address data-in byte 3 data polling timing diagram address a17-0 dq7 we oe ce x x x x t cep t oeh t oep t oes t ec t bp or an an an an
w49f002u - 18 - timing waveforms, continued toggle bit timing diagram address a17-0 dq6 ce oe we t oeh t oes t bp or t ec boot block lockout enable timing diagram sb2 sb1 sb0 address a17-0 dq7-0 ce oe we sb3 sb4 sb5 six byte code for boot block lockout feature enable t ec t wp t wph 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 40
w49f002u publication release date: april 2000 - 19 - revision a2 timing waveforms, conti nued chip erase timing diagram sb2 sb1 sb0 address a17-0 dq7-0 ce oe we sb3 sb4 sb5 internal erase starts six-byte code for 5v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10 sector erase timing diagram sb2 sb1 sb0 address a17-0 dq7-0 ce oe we sb3 sb4 sb5 internal erase starts six-byte code for 5v-only software main memory erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa sa aa 55 80 aa 55 30 sa = sector address
w49f002u - 20 - ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package cy cle w49f002u - 70b 70 50 100 (cmos) 32 - pin dip 10k w49f002u - 90b 90 50 100 (cmos) 32 - pin dip 10k w49f002u - 12b 120 50 100 (cmos) 32 - pin dip 10k w49f002ut70b 70 50 100 (cmos) 32 - pin tsop (8 mm 20 mm) 10k w49f002ut90b 90 50 100 (cmos) 32 - pin tsop (8 mm 20 mm) 10k w49f002ut12b 120 50 100 (cmos) 32 - pin tsop (8 mm 20 mm) 10k w49f002up70b 70 50 100 (cmos) 32 - pin plcc 10k w49f002up90b 90 50 100 (cmos) 32 - pin plcc 10k w49f002up12b 120 50 100 (cmos) 32 - pin plcc 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. winbond withholds a boot block options for bottom boot use. please contact winbond faes for detail information.
w49f002u publication release date: april 2000 - 21 - revision a2 package dimensions 32 - pin p - dip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32 - pin plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.9 5 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.51 0 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
w49f002u - 22 - package dimensions, continued 32 - pin tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) q min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm q __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
w49f002u publication release date: april 2000 - 23 - revision a2 version history version date page description a1 nov. 1999 - renamed from w49f002/b/u/n a2 apr. 2000 1, 13 - 15, 20 add the 120 ns bin 14 change tbp(typ.) from 10 m s to 35 m s change tec(max.) from 1 sec to 0.2 sec headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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